This invention relates, generally, to digital logic circuits and, in particular, to an arbitration circuit.
Digital logic circuitry finds a variety of uses in digital computers and digital systems. Digital circuits which can be defined in one of two logic states can be used to indicate system-level-states, such as the occurrence/non-occurrence of an event, or the busy/ready status of a resource.
In asynchronous systems, various sub-systems must interact at times, e.g., a request for access to a bus or a memory access, and a decision as to which sub-system request occurs first, or should be given priority, must be made. For proper system operation, it is essential that the correct decision be made consistently and reliably. An error in the decision may result in allowing two peripheral units simultaneous access to a memory or simultaneous access to a system bus.
Thus, arbitration logic circuts are implemented in an attempt to avoid erroneous decisions which can result in the problems mentioned above, mainly two sub-systems given access to a bus or allowed access to a memory sub-system. Hence, it is highly desirable to provide an arbitration circuit which is simple, reliable, and arbitrates in a very short time between simultaneous or near simultaneous requests for access to a memory bus. The present invention implements an arbitration circuit which achieves the desired speed, reliability and simplicity features utilizing common digital circuits.